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HM-6642
March 1997
512 x 8 CMOS PROM
Description
The HM-6642 is a 512 x 8 CMOS NiCr fusible link Programmable Read Only Memory in the popular 24 pin, byte wide pinout. Synchronous circuit design techniques combine with CMOS processing to give this device high speed performance with very low power dissipation. On-chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structures, such as the 8085. The output enable controls, both active low and active high, further simplify microprocessor system interfacing by allowing output data bus control independent of the chip enable control. The data output latches allow the use of the HM-6642 in high speed pipelined architecture systems, and also in synchronous logic replacement functions. Applications for the HM-6642 CMOS PROM include low power handheld microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, processor control store, and synchronous logic replacement. All bits are manufactured storing a logical "0" and can be selectively programmed for a logical "1" at any bit location.
Features
* Low Power Standby and Operating Power - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100A - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz * Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 120/200ns * Industry Standard Pinout * Single 5.0V Supply * CMOS/TTL Compatible Inputs * Field Programmable * Synchronous Operation * On-Chip Address Latches * Separate Output Enable
Ordering Information
PACKAGE SBDIP SMD# SLIM SBDIP SMD# CLCC SMD# TEMPERATURE RANGE -40oC to +85oC -55oC to +125oC -40oC to +85oC -55oC to +125oC -40oC to +85oC -55oC to +125oC 120ns HM1-6642B-9 5962-8869002JA HM6-6642B-9 5962-8869002LA 5962-88690023A 200ns HM1-6642-9 5962-8869001JA HM6-6642-9 5962-8869001LA HM4-6642-9 5962-88690013A PKG. NO. D24.6 D24.6 D24.3 D24.3 J28.A J28.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3012.1
6-1
HM-6642 Pinouts
HM-6642 (SBDIP) TOP VIEW
A6 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 VCC 23 A8 22 G1 21 G2 20 G3 19 E 18 P 17 Q7 16 Q6 NC 15 Q5 14 Q4 13 Q3 Q0 11 12 Q1 13 Q2 14 GND 15 NC 16 Q3 17 Q4 18 10 20 19 Q7 Q6 A2 A1 A0 7 8 9 23 22 21 E P NC A4 A3 5 6 A5
HM-6642 (CLCC) TOP VIEW
VCC NC G1 A7 A8
PIN DESCRIPTION PIN NC
25 24 G2 G3
DESCRIPTION No Connect Address Inputs Chip Enable Data Output Power (+5V) Output Enable Program Enable
4
3
2
1
28
27
26
A0-A8 E Q VCC G1, G2, G3 P (Note)
NOTE: P should be hardwired to GND except during programming.
Functional Diagram
A8 A7 A6 A5 A4 A3 LATCHED ADDRESS REGISTER 6 A 6 GATED ROW DECODER 64 64 x 64 MATRIX ALL LINES POSITIVE LOGIC - ACTIVE HIGH THREE STATE BUFFERS: OUTPUT ACTIVE A HIGH 8 A A2 A1 A0 LATCHED ADDRESS REGISTER 3 A 3 D E 8-BIT DATA LATCH GATED COLUMN DECODER 8 8 8 8 8 8 8 DATA LATCHES: Q=D L HIGH Q LATCHES ON RISING EDGE OF E ADDRESS LATCHES AND GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF E P SHOULD BE HARDWIRED TO GND EXCEPT DURING PROGRAMMING A
G1 G2 G3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
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Q5
HM-6642 Programming
Introduction The HM-6642 is a 512 word by 8-bit field Programmable Read Only Memory utilizing nicrome fusible links as programmable memory elements. Selected memory locations are permanently changed from their manufactured state, of all low (VOL) to a logical high (VOH), by the controlled application of programming potentials and pulses. Careful adherence to the following programming specifications will result in high programming yield. Both high VCC (6.0V) and low VCC (4.0V) verify cycles are specified to assure the integrity of the programmed fuse. This programming specification, although complete, does not preclude rapid programming. The worst case programming time required is 37.4 seconds, and typical programming time can be approximately 4 seconds per device. The chip (E) and output enable (G) are used during the programming procedure. On PROMs which have more than one output enable control G3 is to be used. The other output enables must be held in the active, or enabled, state throughout the entire programming sequence. The programmer designer is advised that all pins of the programmer's socket should be at ground potential when the PROM is inserted into the socket. VCC must be applied to the PROM before any input or output pin is allowed to rise (See Note). Overall Programming Procedure 1. The address of the first bit to be programmed is presented, and latched by the chip enable (E) falling edge. The output is disabled by taking the output enable G Low: The programming pin is enabled by taking (P) high. 2. VCC is raised to the programming voltage level, 12.5V. 3. All data output pins are pulled up to VCC program. Then the data output pin corresponding to the bit to be programmed is pulled low for 100ms. Only one bit should be programmed at a time. 4. The data output pin is returned to VCC, and the VCC pin is returned to 6.0V. 5. The address of the bit is again presented, and latched by a second chip enable falling edge. 6. The data outputs are enabled, and read, to verify that the bit was successfully programmed. a). If verified, the next bit to be programmed is addressed and programmed. b). If not verified, the programs verify sequence is repeated up to 8 times total. 7. After all bits to be programmed have been verified at 6.0V, the VCC is lowered to 4.0V and all bits are verified. a). If all bits verify, the device is properly programmed. b). If any bit fails to verify, the device is rejected. Programming System Requirements 1. The power supply for the device to be programmed must be able to be set to three voltages: 4.0V, 6.0V, 12.5V. This supply must be able to supply 500mA average, and 1A dynamic, currents to the PROM during programming. The power supply rise fall times when switching between voltages must be no quicker than 1ms. 2. The address drivers must be able to supply a VIH of 4.0V and 6.0V and VIL when the system is at programming voltages. (See Note) 3. The control input buffers must be able to maintain input voltage levels of 70% and 20% VCC for VIH and VIL levels, respectively. Notice that chip enable (E) and G does not require a pull up to programming voltage levels. The program control (P) must switch from ground to VIH and from VIH to the VCC PGM level. (See Note) 4. The data input buffers must be able to sink up to 3mA from the PROM's output pins without rising more than 0.7V above ground, be able to hold the other outputs high with a current source capability of 0.5mA to 2.0mA, and not interfere with the reading and verifying of the data output of the PROM. Notice that a bit to be programmed is changed from a low state (VOL) to high (VOH) by pulling low on the output pin. A suggested implementation is open collector TTL buffers (or inverters) with 4.7k pull up resistors to VCC. (See Note)
NOTE: Never allow any input or output pin to rise more than 0.3V above VCC, or fall more than 0.3V below ground.
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HM-6642 Background Information HM-6642 Programming
PROGRAMMING SPECIFICATIONS LIMITS SYMBOL VCC PROG VCCN VCC LV ICC ICC Peak PROM INPUT PINS VOL VOH IOL IOH Output Low Voltage (To PROM) Output High Voltage (To PROM) Output Sink Current (At VOL) Output Source Current (At VOH) -0.3 70% VCC 0.01 0.01 GND VCC 20% VCC VCC +0.3 V V mA mA PARAMETER Programming VCC Operating VCC Special Verify VCC System ICC Capability Transient ICC Capability MIN 12.0 4.5 4.0 500 1.0 TYP 12.0 5.5 MAX 12.5 5.5 6.0 UNITS V V V mA A
PROM DATA OUTPUT PINS VOL VOH IOL IOH tD tR tF TEHEL TAVEL TELQV tpw tIP TA Output Low Voltage (To PROM) Output High Voltage (To PROM) Output Sink Current (At VOL) Output Source Current (At VOH) Delay Time Rise Time Fall Time Chip Enable Pulse Width Address Valid to Chip Enable Low Time Chip Enable Low to Output Valid Time Programming Pulse Width Input Leakage at VCC = VCC PROG Ambient Temperature -0.3 70% VCC 3.0 0.5 1.0 1.0 1.0 500 500 90 -10 GND VCC 1.0 1.0 10.0 10.0 100 +1.0 25 0.7 VCC +0.3 2.0 10.0 10.0 500 110 10 V V mA mA s s s ns ns ns s A
oC
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HM-6642
PROGRAMMING VCC PROG VIH VIL VIH VIL tD G VCC PROG VIH VIL VCC PROG VIH VIL VCC PROG VCC GND VCC PROG VIH/VOH VIL/VOL tR tD
VERIFY
A
VALID tD
VALID TEHEL
E
tD
P
tD
VCC
tD
tPW
tD
tF READ DATA
Q
FIGURE 1. HM-6642 PROGRAMMING CYCLE
A
VIH VIL TAVEL VIH VIL TEHEL 6.0V 5.0V 4.0V
VALID TEHEL TEHEL
E
tD
tD
VCC
0.0V TELQV VOH VOL TELQV TELQV
Q
READ
READ
READ
FIGURE 2. HM-6642 POST PROGRAMMING VERIFY CYCLE
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HM-6642
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . . . 5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance JA JC SBDIP Package . . . . . . . . . . . . . . . . . . 52oC/W 14oC/W Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 70oC/W 19oC/W CLCC Package . . . . . . . . . . . . . . . . . . 58oC/W 14oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s)+300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-6642B-9, HM-6642-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1680 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
VCC = 5V 10%; TA = -40oC to +85oC (HM-6642B-9, HM-6642-9) LIMITS
SYMBOL ICCSB ICCOP II IOZ VIL VIH VOL VOH1 VOH2
PARAMETER Standby Supply Current Operating Supply Current (Note 3) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage (Note 2)
MIN -1.0 -1.0 -0.3 2.4 2.4 VCC - 1.0
MAX 100 20 +1.0 +1.0 0.8 VCC + 0.3 0.4 -
UNITS A mA A A V V V V V
TEST CONDITIONS IO = 0, VI = VCC or GND, VCC = 5.5V f = 1MHz, IO = 0, VI = VCC or GND, VCC = 5.5V GND VI VCC, VCC = 5.5V GND VO VCC, VCC = 5.5V VCC = 4.5V VCC = 5.5V IOL = 3.2mA, VCC = 4.5V IOH = -1.0mA, VCC = 4.5V IOH = -100A, VCC = 4.5V
AC Electrical Specifications
LIMITS HM-6642B-9 SYMBOL (1) TELQV (2) TAVQV (3) TGVQV (4) TGVQX (5) TGXQZ (6) TELEH (7) TELEL (8) TEHEL (9) TAVEL (10) TELAX PARAMETER Chip Enable Access Time Address Access Time (TAVQV = TELQV + TAVEL) Output Enable Access Time Output Enable Time Output Disable Time Chip Enable Pulse Negative Width Read Cycle Time Chip Enable Pulse Positive Width Address Setup Time Address Hold Time MIN 5 120 160 40 20 25 MAX 120 140 50 50 50 HM-6642-9 MIN 5 200 350 150 20 60 MAX 200 220 150 150 150 UNITS ns ns ns ns ns ns ns ns ns ns TEST CONDITIONS Notes 1, 4 Notes 1, 4 Notes 1, 4 Notes 2, 4 Notes 2, 4 Notes 1, 4 Notes 1, 4 Notes 1, 4 Notes 1, 4 Notes 1, 4
6-6
HM-6642
Capacitance
TA = +25oC LIMITS SYMBOL CI CO NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. Typical derating 5mA/MHz increase in ICCOP. 4. VCC = 4.5V and 5.5V. PARAMETER Input Capacitance (Note 2) Output Capacitance (Note 2) MIN MAX 10.0 12.0 UNITS pF pF TEST CONDITIONS f = 1MHz, All Measurements Reference Device Ground
Switching Waveform
(2) TAVQV TELAX (10) ADD VALID (8) TEHEL E TELQV (1) Q TGVQX (4) TGXQZ (5) G (NOTE) TIME REFERENCE -1 0 1 2 3 456 TGVQV (3) DATA VALID TGXQZ (5) TELEL (7) TELEH (6) TEHEL (8) TAVEL (9) NEXT ADD
(9) TAVEL A
NOTE: G has the same timing as G except signal is inverted. FIGURE 3. READ CYCLE
Test Load Circuit
DUT CL (NOTE) IOH NOTE: TEST HEAD CAPACITANCE, INCLUDES STRAY AND JIG CAPACITANCE
1.5V
IOL
EQUIVALENT CIRCUIT
6-7
HM-6642
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
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